1. Field of the Invention
The present invention relates to computer systems, and in particular, to a self-corrective system and method of loading program code into a memory having one or more defective memory cells.
2. Description of the Prior Art
Memory chips, such as dynamic random access memory (DRAM) devices, have now reached a high level of technological advancement in which these devices are now capable of storing over a million bits of information in a single semiconductor chip. Since each bit requires at least one transistor and associated circuitry to implement, even the best manufacturing fabrication lines will still turn out memory devices that have numerous bad parts, or memory cells. In the past, memory devices with bad memory cells were typically discarded, thereby resulting in waste and economic loss.
To address this problem, attempts were made to cause a memory device having some defective memory cells to behave as a defect-free memory device. One approach involved the actual repair of defective memory cells or addresses. Actual repair can be accomplished by providing a redundant or substitute memory to store data or program code intended for the defective memory cells or addresses in the memory device. Associated circuitry or software is provided to "link" the defective cells from the regular memory cells to the designated replacement cells in the redundant memory. Laser repair is used to "link" the defective addresses to the designated replacement addresses. Unfortunately, the provision of a redundant memory requires the inclusion of both the redundant memory and additional circuitry, which complicates the design and increases the cost of the memory device. In addition, this approach does not adequately address the situation where either or both the redundant memory and the additional circuitry may be defective.
Yet other attempts have provided memory devices that were both self-testing and self-correcting, such that the efficacy of regular memory cells can be tested while the memory device is in use, and any defective cells can be repaired or corrected by assigning corresponding replacement cells from the redundant memory to replace the defective cells. The location of defective memory cells can be located by any known testing procedure, such as, for example, by alternatively writing "1" and "0" in each bit location and then verifying the accuracy of the results. Again, these memory devices experience the same problems described above.
In addition, conventional memory devices that are provided in the form of an integrated circuit (IC) chip are typically put through an extensive testing procedure during manufacture thereof. FIG. 1 illustrates an example of such a testing procedure used for a single-chip microcomputer. Extensive testing of both the logic functions and the memory cells are performed at both the wafer level and at the assembled-package level, such as during steps 2, 5 and 7 of FIG. 1. Laser repair (step 3) can also be performed after the wafer-level testing of step 2.
Unfortunately, the testing of on-chip memory is very time-consuming since every memory cell must be tested. In contrast, the testing of logic functions on a chip is less intensive. Therefore, the testing of on-chip memory significantly increases the cost of manufacturing the memory devices.